Using -Oline -j 72 W=1 redirect to /tmp/tmp.98viSOT5c2 and /tmp/tmp.rpl3Dzyh64
CC=ccache gcc
gcc (GCC) 14.2.1 20240912 (Red Hat 14.2.1-3)
Tree base:
19e8d01a6926 ("dpll: add clock quality level attribute and op")
Skip baseline build, not the first patch and no Kconfig updates
Building the tree before the patch
make[1]: Entering directory '/home/nipa/net-next/wt-0/build_32bit'
  GEN     Makefile
#
# configuration written to .config
#
make[1]: Leaving directory '/home/nipa/net-next/wt-0/build_32bit'
  SYNC    include/config/auto.conf
  GEN     Makefile
  GEN     Makefile
  CALL    ../scripts/checksyscalls.sh
  CHK     kernel/kheaders_data.tar.xz
  CC [M]  drivers/net/ethernet/mellanox/mlx5/core/dpll.o
  LD [M]  drivers/net/ethernet/mellanox/mlx5/core/mlx5_dpll.o
  MODPOST Module.symvers
Kernel: arch/x86/boot/bzImage is ready  (#5703)
  LD [M]  drivers/net/ethernet/mellanox/mlx5/core/mlx5_dpll.ko
Building the tree with the patch
make[1]: Entering directory '/home/nipa/net-next/wt-0/build_32bit'
  GEN     Makefile
#
# configuration written to .config
#
make[1]: Leaving directory '/home/nipa/net-next/wt-0/build_32bit'
  SYNC    include/config/auto.conf
  GEN     Makefile
  GEN     Makefile
  CALL    ../scripts/checksyscalls.sh
  CHK     kernel/kheaders_data.tar.xz
  CC [M]  drivers/net/ethernet/mellanox/mlx5/core/dpll.o
  LD [M]  drivers/net/ethernet/mellanox/mlx5/core/mlx5_dpll.o
  MODPOST Module.symvers
Kernel: arch/x86/boot/bzImage is ready  (#5703)
  CC [M]  drivers/net/ethernet/mellanox/mlx5/core/mlx5_dpll.mod.o
  LD [M]  drivers/net/ethernet/mellanox/mlx5/core/mlx5_dpll.ko