WARNING: line length of 81 exceeds 80 columns
#64: FILE: drivers/cxl/core/port.c:792:
+				 component_reg_phys, &dport->port->capabilities);

total: 0 errors, 1 warnings, 0 checks, 249 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 89273ed64c03 ("cxl: add capabilities field to cxl_dev_state and cxl_port") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT BAD_REPORTED_BY_LINK CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 1 warnings, 0 checks, 249 lines checked