WARNING: please write a help paragraph that fully describes the config symbol
#40: FILE: drivers/clk/Kconfig:91:
+config COMMON_CLK_RP1
+	tristate "Raspberry Pi RP1-based clock support"
+	depends on PCI || COMPILE_TEST
+	depends on COMMON_CLK
+	help
+	  Enable common clock framework support for Raspberry Pi RP1.
+	  This mutli-function device has 3 main PLLs and several clock
+	  generators to drive the internal sub-peripherals.
+

WARNING: line length of 88 exceeds 80 columns
#298: FILE: drivers/clk/clk-rp1.c:229:
+#define DIV_INT_8BIT_MAX		GENMASK(7, 0)	/* max divide for most clocks */

WARNING: line length of 85 exceeds 80 columns
#299: FILE: drivers/clk/clk-rp1.c:230:
+#define DIV_INT_16BIT_MAX		GENMASK(15, 0)	/* max divide for GPx, PWM */

WARNING: line length of 84 exceeds 80 columns
#300: FILE: drivers/clk/clk-rp1.c:231:
+#define DIV_INT_24BIT_MAX               GENMASK(23, 0)	/* max divide for CLK_SYS */

WARNING: line length of 82 exceeds 80 columns
#549: FILE: drivers/clk/clk-rp1.c:480:
+	struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);

WARNING: line length of 82 exceeds 80 columns
#559: FILE: drivers/clk/clk-rp1.c:490:
+	struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);

WARNING: line length of 81 exceeds 80 columns
#572: FILE: drivers/clk/clk-rp1.c:503:
+		clockman_write(clockman, data->cs_reg, 1 << PLL_CS_REFDIV_SHIFT);

WARNING: line length of 82 exceeds 80 columns
#596: FILE: drivers/clk/clk-rp1.c:527:
+	struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);

WARNING: line length of 93 exceeds 80 columns
#625: FILE: drivers/clk/clk-rp1.c:556:
+		((u64)parent_rate * (((u64)fbdiv_int << 24) + fbdiv_frac) + (1 << 23)) >> 24;

WARNING: line length of 82 exceeds 80 columns
#636: FILE: drivers/clk/clk-rp1.c:567:
+	struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);

WARNING: line length of 82 exceeds 80 columns
#676: FILE: drivers/clk/clk-rp1.c:607:
+	struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);

WARNING: line length of 93 exceeds 80 columns
#685: FILE: drivers/clk/clk-rp1.c:616:
+		((u64)parent_rate * (((u64)fbdiv_int << 24) + fbdiv_frac) + (1 << 23)) >> 24;

WARNING: line length of 82 exceeds 80 columns
#703: FILE: drivers/clk/clk-rp1.c:634:
+	struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);

WARNING: line length of 86 exceeds 80 columns
#730: FILE: drivers/clk/clk-rp1.c:661:
+		abs_diff(DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate);

WARNING: line length of 82 exceeds 80 columns
#1052: FILE: drivers/clk/clk-rp1.c:983:
+		       clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE);

WARNING: line length of 87 exceeds 80 columns
#1056: FILE: drivers/clk/clk-rp1.c:987:
+			       clockman_read(clockman, GPCLK_OE_CTRL) | data->oe_mask);

WARNING: line length of 83 exceeds 80 columns
#1070: FILE: drivers/clk/clk-rp1.c:1001:
+		       clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE);

WARNING: line length of 88 exceeds 80 columns
#1074: FILE: drivers/clk/clk-rp1.c:1005:
+			       clockman_read(clockman, GPCLK_OE_CTRL) & ~data->oe_mask);

WARNING: line length of 94 exceeds 80 columns
#1202: FILE: drivers/clk/clk-rp1.c:1133:
+		clockman_write(clockman, data->div_frac_reg, div << (32 - CLK_DIV_FRAC_BITS));

CHECK: Alignment should match open parenthesis
#1539: FILE: drivers/clk/clk-rp1.c:1470:
+	if (WARN_ON_ONCE(clock_data->num_std_parents > AUX_SEL &&
+	    strcmp("-", clock_data->parents[AUX_SEL])))

CHECK: Lines should not end with a '('
#1589: FILE: drivers/clk/clk-rp1.c:1520:
+	[RP1_PLL_SYS_CORE] = REGISTER_PLL_CORE(

CHECK: Lines should not end with a '('
#1597: FILE: drivers/clk/clk-rp1.c:1528:
+	[RP1_PLL_AUDIO_CORE] = REGISTER_PLL_CORE(

CHECK: Lines should not end with a '('
#1605: FILE: drivers/clk/clk-rp1.c:1536:
+	[RP1_PLL_VIDEO_CORE] = REGISTER_PLL_CORE(

CHECK: Lines should not end with a '('
#1613: FILE: drivers/clk/clk-rp1.c:1544:
+	[RP1_PLL_SYS] = REGISTER_PLL(

CHECK: Lines should not end with a '('
#1620: FILE: drivers/clk/clk-rp1.c:1551:
+	[RP1_PLL_SYS_PRI_PH] = REGISTER_PLL_PH(

CHECK: Lines should not end with a '('
#1629: FILE: drivers/clk/clk-rp1.c:1560:
+	[RP1_PLL_SYS_SEC] = REGISTER_PLL_DIV(

CHECK: Lines should not end with a '('
#1636: FILE: drivers/clk/clk-rp1.c:1567:
+	[RP1_CLK_ETH_TSU] = REGISTER_CLK(

total: 0 errors, 19 warnings, 8 checks, 1684 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 7ca378677153 ("clk: rp1: Add support for clocks provided by RP1") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT BAD_REPORTED_BY_LINK CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 19 warnings, 8 checks, 1684 lines checked