diff --git a/home/nipa/nipa_out/877763/ynl/old-code/dpll-user.c b/home/nipa/nipa_out/877763/ynl/new-code/dpll-user.c
index 4b7bd4c469de..2c6b6893c819 100644
--- a/home/nipa/nipa_out/877763/ynl/old-code/dpll-user.c
+++ b/home/nipa/nipa_out/877763/ynl/new-code/dpll-user.c
@@ -140,6 +140,19 @@ const char *dpll_pin_capabilities_str(enum dpll_pin_capabilities value)
 	return dpll_pin_capabilities_strmap[value];
 }
 
+static const char * const dpll_pin_e_sync_pulse_strmap[] = {
+	[0] = "none",
+	[1] = "25-75",
+	[2] = "75-25",
+};
+
+const char *dpll_pin_e_sync_pulse_str(enum dpll_pin_e_sync_pulse value)
+{
+	if (value < 0 || value >= (int)YNL_ARRAY_SIZE(dpll_pin_e_sync_pulse_strmap))
+		return NULL;
+	return dpll_pin_e_sync_pulse_strmap[value];
+}
+
 /* Policies */
 const struct ynl_policy_attr dpll_frequency_range_policy[DPLL_A_PIN_MAX + 1] = {
 	[DPLL_A_PIN_FREQUENCY_MIN] = { .name = "frequency-min", .type = YNL_PT_U64, },
@@ -217,6 +230,9 @@ const struct ynl_policy_attr dpll_pin_policy[DPLL_A_PIN_MAX + 1] = {
 	[DPLL_A_PIN_PHASE_ADJUST] = { .name = "phase-adjust", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_PHASE_OFFSET] = { .name = "phase-offset", .type = YNL_PT_U64, },
 	[DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET] = { .name = "fractional-frequency-offset", .type = YNL_PT_UINT, },
+	[DPLL_A_PIN_E_SYNC_FREQUENCY] = { .name = "e-sync-frequency", .type = YNL_PT_U64, },
+	[DPLL_A_PIN_E_SYNC_FREQUENCY_SUPPORTED] = { .name = "e-sync-frequency-supported", .type = YNL_PT_NEST, .nest = &dpll_frequency_range_nest, },
+	[DPLL_A_PIN_E_SYNC_PULSE] = { .name = "e-sync-pulse", .type = YNL_PT_U32, },
 };
 
 const struct ynl_policy_nest dpll_pin_nest = {
@@ -737,6 +753,7 @@ void dpll_pin_get_rsp_free(struct dpll_pin_get_rsp *rsp)
 	for (i = 0; i < rsp->n_parent_pin; i++)
 		dpll_pin_parent_pin_free(&rsp->parent_pin[i]);
 	free(rsp->parent_pin);
+	dpll_frequency_range_free(&rsp->e_sync_frequency_supported);
 	free(rsp);
 }
 
@@ -843,6 +860,25 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
 				return YNL_PARSE_CB_ERROR;
 			dst->_present.fractional_frequency_offset = 1;
 			dst->fractional_frequency_offset = ynl_attr_get_sint(attr);
+		} else if (type == DPLL_A_PIN_E_SYNC_FREQUENCY) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.e_sync_frequency = 1;
+			dst->e_sync_frequency = ynl_attr_get_u64(attr);
+		} else if (type == DPLL_A_PIN_E_SYNC_FREQUENCY_SUPPORTED) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.e_sync_frequency_supported = 1;
+
+			parg.rsp_policy = &dpll_frequency_range_nest;
+			parg.data = &dst->e_sync_frequency_supported;
+			if (dpll_frequency_range_parse(&parg, attr))
+				return YNL_PARSE_CB_ERROR;
+		} else if (type == DPLL_A_PIN_E_SYNC_PULSE) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.e_sync_pulse = 1;
+			dst->e_sync_pulse = ynl_attr_get_u32(attr);
 		}
 	}
 
@@ -951,6 +987,7 @@ void dpll_pin_get_list_free(struct dpll_pin_get_list *rsp)
 		for (i = 0; i < rsp->obj.n_parent_pin; i++)
 			dpll_pin_parent_pin_free(&rsp->obj.parent_pin[i]);
 		free(rsp->obj.parent_pin);
+		dpll_frequency_range_free(&rsp->obj.e_sync_frequency_supported);
 		free(rsp);
 	}
 }
@@ -1003,6 +1040,7 @@ void dpll_pin_get_ntf_free(struct dpll_pin_get_ntf *rsp)
 	for (i = 0; i < rsp->obj.n_parent_pin; i++)
 		dpll_pin_parent_pin_free(&rsp->obj.parent_pin[i]);
 	free(rsp->obj.parent_pin);
+	dpll_frequency_range_free(&rsp->obj.e_sync_frequency_supported);
 	free(rsp);
 }
 
@@ -1046,6 +1084,8 @@ int dpll_pin_set(struct ynl_sock *ys, struct dpll_pin_set_req *req)
 		dpll_pin_parent_pin_put(nlh, DPLL_A_PIN_PARENT_PIN, &req->parent_pin[i]);
 	if (req->_present.phase_adjust)
 		ynl_attr_put_s32(nlh, DPLL_A_PIN_PHASE_ADJUST, req->phase_adjust);
+	if (req->_present.e_sync_frequency)
+		ynl_attr_put_u64(nlh, DPLL_A_PIN_E_SYNC_FREQUENCY, req->e_sync_frequency);
 
 	err = ynl_exec(ys, nlh, &yrs);
 	if (err < 0)
diff --git a/home/nipa/nipa_out/877763/ynl/old-code/dpll-user.h b/home/nipa/nipa_out/877763/ynl/new-code/dpll-user.h
index 90dffd671d7c..4d83cb2be604 100644
--- a/home/nipa/nipa_out/877763/ynl/old-code/dpll-user.h
+++ b/home/nipa/nipa_out/877763/ynl/new-code/dpll-user.h
@@ -25,6 +25,7 @@ const char *dpll_pin_type_str(enum dpll_pin_type value);
 const char *dpll_pin_direction_str(enum dpll_pin_direction value);
 const char *dpll_pin_state_str(enum dpll_pin_state value);
 const char *dpll_pin_capabilities_str(enum dpll_pin_capabilities value);
+const char *dpll_pin_e_sync_pulse_str(enum dpll_pin_e_sync_pulse value);
 
 /* Common nested types */
 struct dpll_frequency_range {
@@ -364,6 +365,9 @@ struct dpll_pin_get_rsp {
 		__u32 phase_adjust_max:1;
 		__u32 phase_adjust:1;
 		__u32 fractional_frequency_offset:1;
+		__u32 e_sync_frequency:1;
+		__u32 e_sync_frequency_supported:1;
+		__u32 e_sync_pulse:1;
 	} _present;
 
 	__u32 id;
@@ -383,6 +387,9 @@ struct dpll_pin_get_rsp {
 	__s32 phase_adjust_max;
 	__s32 phase_adjust;
 	__s64 fractional_frequency_offset;
+	__u64 e_sync_frequency;
+	struct dpll_frequency_range e_sync_frequency_supported;
+	enum dpll_pin_e_sync_pulse e_sync_pulse;
 };
 
 void dpll_pin_get_rsp_free(struct dpll_pin_get_rsp *rsp);
@@ -453,6 +460,7 @@ struct dpll_pin_set_req {
 		__u32 prio:1;
 		__u32 state:1;
 		__u32 phase_adjust:1;
+		__u32 e_sync_frequency:1;
 	} _present;
 
 	__u32 id;
@@ -465,6 +473,7 @@ struct dpll_pin_set_req {
 	unsigned int n_parent_pin;
 	struct dpll_pin_parent_pin *parent_pin;
 	__s32 phase_adjust;
+	__u64 e_sync_frequency;
 };
 
 static inline struct dpll_pin_set_req *dpll_pin_set_req_alloc(void)
@@ -530,6 +539,13 @@ dpll_pin_set_req_set_phase_adjust(struct dpll_pin_set_req *req,
 	req->_present.phase_adjust = 1;
 	req->phase_adjust = phase_adjust;
 }
+static inline void
+dpll_pin_set_req_set_e_sync_frequency(struct dpll_pin_set_req *req,
+				      __u64 e_sync_frequency)
+{
+	req->_present.e_sync_frequency = 1;
+	req->e_sync_frequency = e_sync_frequency;
+}
 
 /*
  * Set attributes of a target pin