WARNING: line length of 84 exceeds 80 columns
#34: FILE: drivers/net/ethernet/ti/icssg/icssg_config.h:113:
+#define PRUETH_MAX_RX_FLOWS_SR1			4	/* excluding default flow */

WARNING: line length of 83 exceeds 80 columns
#35: FILE: drivers/net/ethernet/ti/icssg/icssg_config.h:114:
+#define PRUETH_RX_FLOW_DATA_SR1			3       /* highest priority flow */

WARNING: line length of 84 exceeds 80 columns
#37: FILE: drivers/net/ethernet/ti/icssg/icssg_config.h:116:
+#define PRUETH_MAX_RX_MGM_FLOWS_SR1		2	/* excluding default flow */

WARNING: line length of 83 exceeds 80 columns
#53: FILE: drivers/net/ethernet/ti/icssg/icssg_config.h:132:
+	__le32 addr_hi;		/* MSMC Buffer pool base address high. Must be 0 */

WARNING: line length of 81 exceeds 80 columns
#64: FILE: drivers/net/ethernet/ti/icssg/icssg_config.h:143:
+	__le32 rand_seed;	/* Used for the random number generation at fw */

total: 0 errors, 5 warnings, 0 checks, 62 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 267a951532df ("net: ti: icssg-prueth: Add SR1.0-specific configuration bits") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT BAD_REPORTED_BY_LINK CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 5 warnings, 0 checks, 62 lines checked